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september 2001 copyright ? alliance semiconductor. all rights reserved. ? as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 1 of 9 5v/3.3v 128k8 cmos sram (evolutionary pinout) features ? as7c1024 (5v version) as7c31024 (3.3v version) industrial and commercial temperatures organization: 131,072 words 8 bits high speed - 12/15/20 ns address access time - 6, 7,8 ns output enable access time low power consumption: active - 825 mw (c) / max @ 12 ns - 360 mw (as7c31024) / max @ 12 ns low power consumption: standby - 55 mw (as7c1024) / max cmos - 36 mw (as7c31024) / max cmos easy memory expansion with ce1 , ce2, oe inputs ttl/lvttl-compatible, three-state i/o 32-pin jedec standard packages -300 mil soj -400 mil soj - 8 20mm tsop 1 esd protection 2000 volts latch-up current 200 ma logic block diagram 512 256 8 array (1,048,576) sense amp input buffer a10 a11 a12 a13 a14 a15 a16 i/o0 i/o7 oe ce1 we column decoder row decoder control circuit a9 a0 a1 a2 a3 a4 a5 a6 a7 v cc gnd a8 ce2 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v cc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o5 i/o4 i/o3 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd as7c1024 as7c31024 32-pin soj (300 mil) v cc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o7 i/o6 i/o4 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 32-pin (8 x 20mm) tsop 1 i/o2 gnd i/o5 i/o3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32 31 30 29 28 27 26 25 24 23 22 21 as7c1024 as7c31024 20 19 15 16 18 17 32-pin (8 x 13.4mm) stsop 1 32-pin soj (400 mil) selection guide -12 -15 -20 unit maximum address access time 12 15 20 ns maximum output enable access time 6 7 8 ns maximum operating current as7c1024 140 125 110 ma as7c31024 90 80 75 ma maximum cmos standby current as7c1024 10 10 15 ma as7c31024 10 10 15 ma
? as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 2 of 9 functional description the as7c1024 and as7c31024 are high performance cmos 1,048,576-bit static random access memory (sram) devices organized as 131,072 words 8 bits. it is designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 12/15/20 ns with output enable access times (t oe ) of 6, 7,8 ns are ideal for high performance applications. active high and low chip enables (ce1 , ce2) permit easy memory expansion with multiple- bank systems. when ce1 is high or ce2 is low the devices enter standby mode. if inputs are still toggling, the device will consume i sb power. if the bus is static, then full standby power is reached (i sb1 or i sb2 ). for example, the as7c31024 is guaranteed not to exceed 0.33mw under nominal full standby conditions. all devices in this family will retain data when vcc is reduced as low as 2.0v. a write cycle is accomplished by asserting write enable (we ) and both chip enables (ce1 , ce2). data on the input pins i/o0-i/ o7 is written on the rising edge of we (write cycle 1) or the active-to-inactive edge of ce1 or ce2 (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and both chip enables (ce1 , ce2), with write enable (we ) high. the chips drive i/o pins with the data word referenced by the input address. when either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions outside those indicated in the operational sections of this specification i s not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: x = don?t care, l = low, h = high parameter symbol min max unit vol tag e o n v cc relative to gnd as7c1024 v t1 ?0.50 +7.0 v as7c31024 v t1 -0.50 +5.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.0w storage temperature (plastic) t stg ?65 +150 c ambient temperature with v cc applied t bias ?55 +125 c dc current into outputs (low) i out ?20ma ce1 ce2 we oe data mode hxxx high z standby (i sb , i sb1 ) xlxx high z standby (i sb , i sb1 ) l h h h high z output disable (i cc ) lhhl d out read (i cc ) lhlx d in write ( icc )
as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 3 of 9 ? recommended operating conditions ? v il min = ?3.0v for pulse width less than t rc/2 . dc operating characteristics (over the operating range) shaded areas contain advance information. capacitance (f = 1 mhz, t a = 25 c, v cc = nominal) parameter device symbol min nominal max unit supply voltage as7c1024 v cc 4.5 5.0 5.5 v as7c31024 v cc 3.0 3.3 3.6 v input voltage as7c1024 v ih 2.2 ? v cc + 0.5 v as7c31024 v ih 2.0 ? v cc + 0.5 v v il ? ?0.5 ? 0.8 v ambient operating temperature commercial t a 0?70 c industrial t a ?40 ? 85 c parameter sym test conditions device -12 -15 -20 unit min max min max min max input leakage current |i li |v cc = max, v in = gnd to v cc ?1?1?1 a output leakage current |i lo | v cc = max, ce1 = v ih or ce2 = v il , v out = gnd to v cc ?1?1?1 a operating power supply current i cc v cc = max, ce1 = v il , ce2 = v ih , f = f max , i out = 0 ma as7c1024 ? 140 ? 125 ? 110 ma as7c31024 ? 90 ? 80 ? 75 standby power supply current i sb v cc = max, ce1 v ih and/or ce2 v il , v in = v ih or v il , f = f max , i out = 0ma as7c1024 ? 75 ? 65 ? 60 ma as7c31024 ? 50 ? 40 ? 35 i sb1 v cc = max, ce1 v cc ?0.2v v in gnd + 0.2v or v in v cc ?0.2v, f = 0 as7c1024 ? 10 ? 10 ? 15 ma as7c31024 ? 10 ? 10 ? 15 output voltage v ol i ol = 8 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce1 , ce2, we , oe v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 4 of 9 read cycle (over the operating range) key to switching waveforms read waveform 1 (address controlled) read waveform 2 (ce1 , ce2, and oe controlled) parameter symbol -12 -15 -20 unit notes min max min max min max read cycle time t rc 12 ? 15 ? 20 ? ns address access time t aa ?12?15?20ns 3 chip enable (ce1 ) access time t ace1 ?12?15?20ns 3, 12 chip enable (ce2) access time t ace2 ?12?15?20ns 3, 12 output enable (oe ) access time t oe ?6?7?8ns output hold from address change t oh 3?3?3?ns 5 ce1 low to output in low z t clz1 3?3?3?ns4, 5, 12 ce2 high to output in low z t clz2 3?3?3?ns4, 5, 12 ce1 low to output in high z t chz1 ?3?4?5ns4, 5, 12 ce2 low to output in high z t chz2 ?3?4?5ns4, 5, 12 oe low to output in low z t olz 0?0?0?ns 4, 5 oe high to output in high z t ohz ?3?4?5ns 4, 5 power up time t pu 0?0?0?ns4, 5, 12 power down time t pd ?12?15?20ns4, 5, 12 undefined / don?t care falling input rising input address d out data valid t oh t aa t rc supply current ce2 oe d out t oe t olz t ace1 , tace2 t chz1 , t chz2 t clz1 , t clz2 t pu t pd i cc i sb 50% 50% data valid t rc1 ce1 t ohz
as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 5 of 9 ? write cycle (over the operating range) write waveform 1 ( we controlled)
write waveform 2 (ce1 and ce2 controlled)
parameter symbol -12 -15 -20 unit notes min max min max min max write cycle time t wc 12 ? 15 ? 20 ? ns chip enable (ce1 ) to write end t cw1 10 ? 12 ? 12 ? ns 12 chip enable (ce2) to write end t cw2 10 ? 12 ? 12 ? ns 12 address setup to write end t aw 10 ? 12 ? 12 ? ns address setup time t as 0 ? 0 ? 0 ? ns 12 write pulse width t wp 8?9?12?ns write recovery time t wr 0?0?0?ns address hold from end of write t ah 0?0?0?ns data valid to write end t dw 6?9?10?ns data hold time t dh 0?0?0?ns4, 5 write enable to output in high z t wz ?5?5?5ns4, 5 output active from write end t ow 3?3?3?ns4, 5 t aw t ah t wc address we d out t dh t ow t dw t wz t wp t as data valid d in t wr t aw address ce1 we d out t cw1 , t cw2 t wp t dw t dh t ah t wz t wc t as ce2 data valid d in t wr
? as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 6 of 9 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce1 is required to meet i sb specification. 2 this parameter is sampled and not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, and c. 4t clz and t chz are specified with cl = 5pf, as in figure c. transition is measured 500mv from steady-state voltage. 5 this parameter is guaranteed, but not 100% tested. 6we is high for read cycle. 7ce1 and oe are low and ce2 is high for read cycle. 8 address valid prior to or coincident with ce1 transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce1 or we must be high or ce2 low during address transitions. either ce1 or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 ce1 and ce2 have identical timing. 13 c=30pf, except all high z and low z parameters, c=5pf. 255w ? 5v output load: see figure b or figure c. ? input pulse level: gnd to 3.0v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5v. c(14) 320w d out gnd +3.3v 168w thevenin equivalent: d out +1.728v (5v and 3.3v) figure c: 3.3v output load 255w c(14) 480w d out gnd +5v figure b: 5v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns
as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 7 of 9 ? typical dc and ac characteristics supply voltage (v) min max nominal 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb ambient temperature (c) ?55 80 125 35 ?10 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized i cc , i sb normalized supply current i cc , i sb vs. ambient temperature t a vs. supply voltage v cc i cc i sb i cc i sb ambient temperature (c) -55 80 125 35 -10 0.2 1 0.04 5 25 625 normalized isb1 (log scale) normalized supply current i sb1 vs. ambient temperature t a v cc = v cc (nominal) supply voltage (v) min max nominal 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa ambient temperature (c) ?55 80 125 35 ?10 0.8 0.9 1.1 1.2 1.0 1.3 1.4 1.5 normalized access time normalized access time t aa cycle frequency (mhz) 075 100 50 25 0.0 0.2 0.6 0.8 0.4 1.0 1.2 1.4 normalized icc normalized supply current i cc vs. ambient temperature t a vs. cycle frequency 1/t rc , 1/t wc vs. supply voltage v cc t a = 25 c v cc = v cc (nominal) v cc = v cc (nominal) t a = 25 c output voltage (v) v cc 0 20 60 80 40 100 120 140 output source current (ma) output source current i oh output voltage (v) v cc output sink current (ma) output sink current i ol vs. output voltage v ol vs. output voltage v oh 0 20 60 80 40 100 120 140 capacitance (pf) 0 750 1000 500 250 0 5 15 20 10 25 30 35 change in t aa (ns) typical access time change ? t aa vs. output capacitive loading 00 v cc = v cc (nominal) t a = 25 c v cc = v cc (nominal) t a = 25 c v cc = v cc (nominal)
? as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 8 of 9 package dimensions c ea seating b a1 e1 e d e l s plane b a pin 1 seating plane e b e hd d c l a1 a a2 pin 1 pin 32 pin 16 pin 17 pin 1 d e e1 e2 a1 b b a a2 e c 32-pin pdip min in mils max in mils a - 0.180 a1 0.015 - b 0.045 0.055 b 0.015 0.021 c 0.008 0.012 d - 1.571 e 0.300 0.325 e1 0.280 0.295 e0.100 bsc ea 0.330 0.370 l 0.110 0.142 a 0 15 s - 0.043 32-pin soj 300 mil 32-pin soj 400 mil min max min max a - 0.145 - 0.145 a1 0.025 - 0.025 - a2 0.086 0.105 0.086 0.115 b 0.026 0.032 0.026 0.032 b 0.014 0.020 0.015 0.020 c 0.006 0.013 0.007 0.013 d 0.820 0.830 0.820 0.830 e 0.250 0.275 0.360 0.380 e1 0.292 0.305 0.395 0.405 e2 0.330 0.340 0.435 0.445 e 0.050 bsc 0.050 bsc 32-pin tsop 820 mm min in mm max in mm a?1.20 a1 0.05 0.15 a2 0.95 1.05 b 0.17 0.27 c 0.10 0.21 d 18.20 18.60 e 0.50 nominal e 7.80 8.20 hd 19.80 20.20 l 0.50 0.70 0 5
as7c1024 as7c31024 9/19/01; v.1.4 alliance semiconductor p. 9 of 9 ? copyright alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time withou t notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to chang e or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpo se, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life- supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and t he inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use ? ordering codes part numbering system package \ access time vo l t / te m p 12 ns 15 ns 20 ns plastic soj, 300 mil 5v commercial as7c1024-12tjc as7c1024-15tjc as7c1024-20tjc 5v industrial as7c1024-12tji as7c1024-15tji as7c1024-20tji 3.3v commercial as7c31024-12tjc as7c31024-15tjc as7c31024-20tjc 3.3v industrial as7c31024-12tji as7c31024-15tji as7c31024-20tji plastic soj, 400 mil 5v commercial as7c1024-12jc as7c1024-15jc as7c1024-20jc 5v industrial as7c1024-12ji as7c1024-15ji as7c1024-20ji 3.3v commercial AS7C31024-12JC as7c31024-15jc as7c31024-20jc 3.3v industrial as7c31024-12ji as7c31024-15ji as7c31024-20ji tsop 8 20 mm 5v commercial as7c1024-12tc as7c1024-15tc as7c1024-20tc 5v industrial as7c1024-12ti as7c1024-15ti as7c1024-20ti 3.3v commercial as7c31024-12tc as7c31024-15tc as7c31024-20tc 3.3v industrial as7c31024-12ti as7c31024-15ti as7c31024-20ti as7c x 1024 ?xx x x sram prefix blank=5v cmos 3=3.3v cmos device number access time package: tp=pdip 300 mil t=tsop1 820 mm j=soj 400 mil tj=soj 300 mil te m p e r a t u r e r a n g e c = commercial, 0c to 70c i = industrial, -40c to 85c

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